1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method, particularly to a semiconductor device and manufacturing method in which two or more wiring layers are stacked and an interlayer wiring is performed by a via plug, and is used in a semiconductor device in which a low-resistance metal wiring such as copper wiring is used.
2. Description of the Related Art
In recent years, in important parts of a computer or a communication apparatus, large-scale integration (LSI) has frequently been used in which a large number of transistors or resistors are interconnected to achieve an electric circuit, and integrated and formed on one chip. Therefore, performance of the whole apparatus largely depends on that of a single LSI unit. Enhancement of the performance of the LSI unit can be realized by promoting the integration by miniaturizing elements such as the transistors or resistors.
However, by the miniaturization, a problem has become remarkable that RC delay caused by wiring resistance R and inter-wiring capacity C coupling deteriorates a high speed operation of the elements. To solve the problem, it is necessary to reduce the inter-wiring capacity by using an insulating layer material having a small dielectric constant. Moreover, instead of using the insulating material of the small dielectric constant, a method of reducing layer thicknesses of wirings is used to reduce an opposing area of opposite wirings.
However, with advancement of the reduction of the wiring thickness, a wiring resistance increases, and the RC delay is increased. To solve the problem, a low-resistance metal such as copper has been used as the wiring metal. However, when the miniaturization advances, and a wiring width is reduced, a percentage of copper wiring in the whole wiring used in the apparatus decreases. As a result, a reduction effect of the wiring resistance using the copper decreases (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2001-345380).
A cause for the decrease of the percentage of copper in the wiring will is as follows. When a copper wiring is formed in a wiring groove and a via hole coupled to the wiring groove by a dual-damascene process, a barrier metal is first formed and then copper is deposited to form the copper wiring. However, the layer thickness of the barrier metal cannot be assured at side walls of a bottom portion of the via hole, thereby decreasing the reliability of the copper wiring. Accordingly, the barrier metal should be made thick even at the bottom of the via hole and the barrier metal cannot catch up with a reduction ratio of a copper wiring sectional area.
As described above, for a semiconductor device in which the low-resistance metal is used as the wiring metal, with the advancement of the miniaturization and the reduction of the wiring width, the reduction effect of the wiring resistance has been reduced and it is difficult to enhance the reliability of the metal wiring.